- 所有GaN Systems产品的衍生设计产品的可用性
What are your gate drive voltage margins/tolerances?
The most important specification for our devices is a 6V turn-on voltage. We specify a 7V absolute maximum DC voltage but we allow spikes and noise by specifying a 10V transient voltage. For turn-off, depending on the system, we recommend 0V, -3V or -6V. Our negative gate drive is specified at -10V absolute Maximum DC and -20V transient.
Are there dv/dt and di/dt constraints?
No, there are not any dv/dt or di/dt constraints with our GaN. Often, these constraints are related to parasitic PN junction devices (such as in an IGBT) but in our E-HEMT products, there are no parasitic junctions. This is also why our Qrr is zero. Note however that all gate drivers have dv/dt specifications, commonly referred to as Common Mode Transient Immunity (CMTI). GaN Systems recommends that gate drivers with over 150 V/ns are best for driving our devices in high performance systems, while below 100 CMTI is acceptable when the GaN dv/dt is lower such as in consumer products.
How do you drive your GaN with a 12V output controller with driver?
GaN Systems has a proven low cost, small size gate drive solution called EZDrive® which converts a typical 0-12V MOSFET driver output to a -6V to +6V GaN drive. See our Application note GN010, “EZDrive Solution for GaN Systems E-HEMTs”
How do you recommend I use boost, buck power conversion controller ICs that include the driver?
Most of the controllers with an integrated driver can drive GaN Systems GaN with an EZDriveTM circuit, and therefore an additional driver is not needed. Refer to the following for more information: https://gansystems.com/wp-content/uploads/2020/07/GN010_EZDrive-Solution-for-GaN-Systems-GaN-Transistors-_20200715.pdf
Does GaN Systems have a Low Gate to Source Threshold Voltage?
Yes, the threshold voltage of our GaN is 1.7V. For this reason, we do recommend (i) good layout (ii) in higher power systems, driving with a negative voltage such as -3V (which as this webinar shows, also provides lower overall losses)
Is Miller capacitance an issue?
Miller capacitance is one of the design criteria that must be considered, but our application notes and evaluation kits show that with good layout, it can easily be managed and excellent performance with GaN is achieved. Refer to our webinar: Simple Layout Steps for Maximizing GaN Design Performance for more information.
Why does negative turn off voltage lead to lower switching loss?
Negative turn-off voltage leads to a faster turn-off speed. For more information, please refer to the pages 24-27 of “Opportunities and design considerations of GaN HEMTs in ZVS applications.”
Is there a online design tool for GaN power design?
Yes. On the website you will find device SPICE models. Additionally, we have created topology models in PLECS and Circuit Simulation Tools on our site.
Do you have an app note that describes operation to reach higher voltages?
Yes. Please refer to our Papers and Presentations section. You will see a title for 800V EV Traction Inverters. This should get you started and then we can later discuss any questions you may have. In general, our GaN is used in multilevel designs with similar design rules as silicon devices.
How should the two gate pins on your devices be connected? Can they be driven together? What are the design considerations with these two gate pins?
These two gate are designed for easily PCB trace routing; Use one of the 2 gate drive pins only, do not drive both of them.
How is the drive power calculated?
Use the following equation Prive=Vg x Qg x fs; where the Vg is the power rail voltage of the driver, Qg is the device gate charge, and fs is the switching frequency.
Why is the gate drive assymetric?
Usually, a larger Rg(ON) is required to limit the high di/dt during the hard switching on transition, and a smaller Rg(OFF) helps reduce the impact of Miller effect and our lower Vth value.
Do you have a driver solution recommendation for 100% duty cycle like in Buck Boost?
Most gate drive circuits are compatible with 0 to 100% duty cycle. Refer to our gate drive application note.
What is the difference between a conventional driver and a bootstrap gate driver? When do you recommend a bootstrap?
GaN Systems’ gate functions best when driven by 6.0V to turn the device on. Using a conventional driver with a well regulated power rail is best when possible. If using a driver with a bootstrap function, the user should insure that the bootstrap voltage is well regulated. Also, depending on the overall circuit, when GaN devices are used in a half-bridge application, a diode across the lower GaN device can help regulate the bootstrap voltage and prevent the bootstrap voltage from becoming too high. Application note GN010, page 13 describes the use of this diode.
Do you recommend 0V turn off to reduce the reverse conduction losses or must the device be turned on?
During the freewheeling state, we recommend turning-on the GaN to minimize the conduction loss. This is commonly known as synchronous gate drive. The driver should have 0V (or -3V) only during the dead times.
What are the effects with driving your devices at 4.5V?
The GaN transistors can be operated normally, but Rds(ON) will be much higher. The system efficiency and thermal performance will be impacted.
Why do GIT GaN devices need a constant gate current while E-mode FETs by GaN Systems do not?
A GIT device is a current driven transistor similar to a bipolar junction transistor (BJT) due the GIT gate structure. GaN Systems’ gate structure is voltage driven similar to MOSFET.
With high switching speeds, how do you mitigate any issues associated with noise coupling into the gate drive signal?
The layout is important to avoid noise coupled into the gate drive loop and can be easily minimized. For simple steps to optimize the switching performance of GaN, refer to our webinar: Simple Layout Steps for Maximizing GaN Design Performance.
Does the EZdrive circuit compromise gate driving switching speed?
No, the recommended Rg implemented in the EZDrive circuit is the same as in a conventional gate drive circuit, and the impedance of the capacitor could be regarded as short during the switching transition.
Does parasitic gate loop inductance in a discrete GaN solution degrade the switching performance?
No it does not. The worse case experimental results in this webinar show GaN Systems transistors are not sensitive to the gate loop inductance. We do, however, emphasize good layout and low parasitic gate loops generate better performance and lower EMI.
Which gate loop is more important? Turn-on or turn-off?
Both loops are important, however if a trade-off needs to be made, the turn-on should be optimized due to the high di/dt during the switching on process.
Is it essential to parallel a very high resistor across gate and source at gate side?
Yes, usually we put a 10kohm to 100kohm resistor to avoid a floating gate.
Speaker: Juncheng (Lucas) Lu
Applications Engineering Manager at GaN Systems
Juncheng Lu received a B.S. degree from Zhejiang University, Hangzhou, China, and M.S. degree from Kettering University, Michigan, USA. He was a research engineer with Delta Power Electronics Center, Shanghai, China since 2011. Since 2016, he has been with GaN Systems, Inc., Ottawa, Canada. His research interest is wide bandgap devices application, power electronics packaging, high power density power supply, and electric vehicle battery charger. He published more than 20 IEEE/SAE transaction and conference papers and holds 10 U.S. patents / 3 U.S. patents pending.
Moderator: Paul Wiener
VP Strategic Marketing at GaN Systems
Paul Wiener is GaN Systems’ Vice President of Strategic Marketing. Prior to joining GaN Systems, Paul led the power magnetics business unit at Eaton. Paul brings more than 25 years’ experience in operations, sales and marketing, and business development. His experience includes vice president of sales at Fultec Semiconductor Inc. and several management roles at Genoa, BroadLogic, and Raychem.