Why are film capacitors preferred to ceramic caps as decoupling?
We do not prefer film capacitors. Ceramic capacitors are usually preferred for decoupling compared to film capacitors because of their smaller package, which introduces less stray inductance to the power commutation loops.
I did not see a sink mounted on the switches? Were the prototypes mounted without a heatsink to those power levels?
The test boards are designed for pulse test only. In double pulse tests, very little heat less than 1mJ is generated, so we did not apply a heatsink. For practical use, the need for a heatsink should be evaluated. In many cases, customers use the GaN solution because the heat sink can be eliminated.
In the power loop, if the current goes back from the first middle layer, will an extra capacitance form because of the mid-switching point?
Yes, there will be some parasitic capacitance between the top layer and the first middle layer. In practical design, we minimize the area of the switching node to reduce the parasitic capacitance between the drain and the source, and to avoid capacitance between the drain and the gate.
In your double pulse test schematic, you are holding OFF the upper device with -5V on the gate. It is my understanding GaN does not have body diode. How does this current then freewheel after the first pulse?
Although there is no body diode in a GaN HEMT, a GaN HEMT does freewheel current during the deadtime. In reverse conduction mode with Vgs < Vth, the Drain of the GaN will behave as a source, while the source will behave as a drain. When Vgs>Vth, the GaN device will be fully turned on like a Si MOSFET. Please refer to page 5 of our application note GN001 for more information.
I saw you have used 0608 package resistor on gate, don’t they have higher parasitic inductance compared to bigger packages?
Usually, the smaller the package the smaller the inductance. So we choose 0603 in our designs.
Can I use GaN in an active rectifier topology?
Yes. As we have seen Si MOSFETs in this application. A GaN circuit should have higher performance since the GaN does not have reverse recovery and operates with a much faster switching transition.
Do you recommend a gate-source capacitor?
Usually, a Cgs is not needed. However, a Cgs can help filter some noise on Vgs, if the layout is not optimum. So, it may be good to have a footprint for Cgs, and then, after testing, determine if it should be populated.
How to do power loop flux canceling with single sided aluminium pcb?
We use the bottom layer of the driver board to do flux cancellation with the single layer of the aluminum PCB. If you have IEEE access, refer to this link for more information: https://ieeexplore.ieee.org/document/8096647
Which SMD capacitors do you recommend?
We recommend 2220 package, 650V, 0.2-1.0uF ceramic capacitors for decoupling.
Is GaN easy to be paralled and is there anything special to be considered for GaN in parallel?
Yes, GaN is quite easy to parallel. We have reference designs with 2 and 4 GaN HEMTs in parallel. The only difference versus a single GaN device applications is that, for paralleled GaN, we need to make sure the power commutation loop for each paralleled transistor is minimized and symmetric. Refer to the application note GN004 for more information:
Will parasitics affect switching loss?
Yes. For example, the common source inductance will slow down the switching transition or even cause false triggering so as to affect the switching loss. Also the power commutation loop inductance will increase the voltage overshoot on Vds, which will also affect the switching loss. Generally speaking, minimizing parasitic inductance minimizes system loss.
What is the recommended maximum dc bus voltage for a 650 V and 100 V GaNSys device?
The maximum transient voltage less than 1uS for our GaN is 750V. So, as long as the voltage spike is less than 650V, there is no concern. In practical designs, we’ve seen 550V bus-voltage systems using 650V GaN HEMTs without issue. For 100V, the design rule is the same, ensure the peak Vds (greater than) 100V.
Whats the thermal tolerance of a 5*6.6 package? Any estimation?
For GS66516T, the junction to heatsink thermal resistance is about 2°C/W.
What is fastest transition achievable by using GaNSystem devices in applications e.g.
The fastest switching transition is achieved in the Lidar application: the device current increases from 0 to 250A within 1.7nS.
What’s your roadmap? are we going to have GaN more than 100A in the range of 80 or 100v soon?
氮化镓系统 (GaN Systems) is continuously working on new product developments. Please keep watching this information on new products.
Please comment on the reverse conduction capabilities of the GaN and its use in an active rectifier application? Thanks.
Although there are no body diodes in GaN HEMTs, GaN HEMTs freewheel current during the deadtime. In reverse conduction mode with Vgs < Vth, the drain of the GaN will behave as a source, while the source will behave as a drain. When Vgs>Vth, the GaN will be fully turned on like a Si MOSFET. Please refer to the page 5 of GN001 application note for more information.
I thought GaN didn’t have a body diode?
Correct, there are no body diodes in GaN HEMTs, GaN HEMTs freewheel current during deadtime. In reverse conduction mode with Vgs < Vth, the drain of the GaN will behave as a source, while the source will behave as a drain. When Vgs>Vth, the GaN will be fully turned on like a Si MOSFET. Please refer to the page 5 of GN001 Application Note for more information.
Are there devices from GaN systems that are based on bidirectional GaN switches?
No. All these devices mentioned in the webinar are HEMTs – unipolar devices.
Do you think that the low bandwidth of the Rogowski coil current sensor will be up to the work to record the fast changes in the waveform of the current, especially with high switching speeds?
Yes, the bandwidth of Rogowski coil is only 30MHz. If there is some high frequency oscillation, the measurement will miss some details. However, it is good enough to tell if there is abnormal beheviour on the switching waveforms. We compared with 2GHz current shunt SDN-414-10, and the measured waveforms were close enough.
Can you comment on the measurement setup (scope, probes, BW, CMRR?) For the Double pulse test
Yes. i_DS is measured by Rogowski coil ( CWTUM/1/B ). V_DS is measured by isolated probe ( THDP0200 ). The V_GS_L is measured by non-isolated probe TPP1000 with MMCX connectors. Please refer to page 14 of this Layout webinar for more information on the test setup.
In the double pulse test circuit the high side GaN is switched off. Is it better to short-circuit Gate and Source or to have a resistance in between to avoid unwanted oscillations?
We suggest using the high-side driver to turn off the high-side switches to emulate the conditions the power stage will see in the system.
How to do precise V-I alignment in DPT test.
During the switching-on transition, the di/dt of Ids will cause a voltage drop on Vds ( L*di/dt ). We adjust the deskew of probes by matching the start of di/dt of ids and the beginning of the Vds voltage plateau.
In design process, do you use Q3D for qualitative analysis only or also for more accurate prediction of switching behavior?